1. Field of the Invention
The present invention relates to a stacking apparatus that stacks chip blocks each having a circuit pattern formed therein, one on top of another so as to assure electrical conduction of electrodes at the individual chip blocks and it also relates to a method for stacking integrated circuit elements.
2. Description of Related Art
Increasingly higher speed and higher performance in CMOS-FET (complementary MOS field effect transistors), the basic component in semiconductor devices today, have been realized through supermicro processing technologies, the primary example of which is lithography. However, beyond the 45 to 65 nm node range (when the DRAM gate half pitch is in the 45 to 65 nm range or beyond) the signal delay in the global wiring used to couple the individual IPs (functional circuit assemblies referred to as intellectual properties) within a chip becomes a crucial issue to be dealt with.
The conventional countermeasures having been taken so far against the signal delay, i.e., the use of wiring constituted with a low-resistance material such as Cu and the use of a low-K material to lower the capacitance, are no longer sufficiently effective and it is now necessary to use an additional compensating circuit (repeater). However, the addition of the compensating circuit inevitably increases the chip size and also increases the power consumption.
At the same time, to keep pace with the increasing Popularity of portable telephones and the like, even smaller LSIs with more diverse functions are required. While the use of three-dimensional integrated circuits achieved by stacking vertically chips having formed therein two-dimensional circuit patterns is becoming increasingly common as a solution to meet those requirements, chips may be conceivably formed through stacking by adopting any of several different modes.
In a first mode, good LSI chips are selected, they are mounted in a low-profile package and then the individual packages are stacked one on top of another. In a second mode, entire chips or wafers are stacked together. Each mode has its own advantages and disadvantages.
While the yield can be sustained at a certain level by adopting the first mode, in which good chips are selected and stacked, the package cost is bound to be significant. In addition, additional connecting wiring must be disposed between the chips and the packages, setting limits to the signal speed that can be achieved.
The second mode may be achieved through either of two different methods. In the first method, after chips are stacked, pads at each chip are connected through wiring (wire-bonded). While this method is very advantageous, in particular in conjunction with inexpensive chips or memory modules, the chips, are ultimately connected through wiring and thus, a wiring delay is bound to occur. For this reason, this option is not suitable for integrated circuits that have to assure high speed transmission. In the second method, through electrodes are mounted in advance in chips and they are directly connected via bumps or the like on the chips.
Accordingly, various next-generation systems for overcoming the limits to miniaturization set in consideration of the device cost and the design capacity requirements by, for instance, adopting special transistor structures, e.g., SOIs (silicon-on-insulator) structures and strained Si channel structures or adopting optical wiring have been put into practical use or have been proposed.
In view of the signal delay occurring in the ultimate mounting area, the Si through electrode system disclosed in U.S. Pat. No. 4,612,083 is considered to be very promising. This system is also effective when adopted in an integrated circuit that transmits signals in parallel at high speed. U.S. Pat. No. 5,270,261 and Japanese Laid Open Patent Publication No. H7-14982 disclose methods for achieving such integrated circuits by stacking wafers having formed therein circuit patterns one on top of another and achieving electrical conduction through direct contact of the chip electrodes formed at the individual wafers.